module top #(
        parameter [31:0] X = 0
) (
        input [31:0] din,
        output [31:0] dout
);
        assign dout = X-din;
endmodule

module top_props #(
        parameter [31:0] X = 0
) (
        input [31:0] dout
);      
        always @* assert (dout != X);
endmodule

bind top top_props #(.X(123456789)) props (.*);

yosys -p 'verific -sv test.sv; hierarchy -chparam X 123123123 -top top; prep -flatten; sat -prove-asserts -show-ports'

Solving problem with 404 variables and 1076 clauses..
SAT proof finished - model found: FAIL!

   ______                   ___       ___       _ _            _ _ 
  (_____ \                 / __)     / __)     (_) |          | | |
   _____) )___ ___   ___ _| |__    _| |__ _____ _| | _____  __| | |
  |  ____/ ___) _ \ / _ (_   __)  (_   __|____ | | || ___ |/ _  |_|
  | |   | |  | |_| | |_| || |       | |  / ___ | | || ____( (_| |_ 
  |_|   |_|   \___/ \___/ |_|       |_|  \_____|_|\_)_____)\____|_|


  Signal Name             Dec       Hex                                 Bin
  --------------- ----------- --------- -----------------------------------
  \din                -333666  fffae89e    11111111111110101110100010011110
  \dout             123456789   75bcd15    00000111010110111100110100010101

module top #(
	parameter [31:0] X = 0
) (
	input [31:0] din,
	output [31:0] dout
);
	assign dout = X-din;
	always @* assert (dout != 123456789);
endmodule

yosys -p 'verific -sv test.sv; hierarchy -chparam X 123123123 -top top; prep -flatten; sat -prove-asserts -show-ports'